

芯原微电子(上海)股份有限公司(芯原)是一家依托自主半导体IP,为客户提供平台化、全方位、一站式芯片定制服务和半导体IP授权服务的企业。
公司成立于2001年,总部位于中国上海,在中国和美国设有5个设计研发中心,全球共有10个销售和客户支持办事处。作为全球客户首选的合作伙伴,芯原全球800多名员工将共同为客户提供设计开发,先进的产品和一流的服务。
为了公司更好的发展,我们离不开员工的全力支持,同时我们也将致力为员工提供良好的薪资、福利、在职培训,以及充分施展个人才华的空间。
请发送您的简历至公司人力资源部:
中国大陆: | hr@verisilicon.com |
海外地区: | hr.us@verisilicon.com |
芯原于每年9月开启年度校园招聘,届时我们将前往华东、华中、华西各大高校开展线下校园宣讲会。招聘面向各大高校电子类、计算机类及自动化相关专业的本科、硕士、及博士应届生。 欢迎大家踊跃参与,期待你们加入芯原! |
|
![]() |
|
宣讲安排及报名方式 | 欢迎关注“芯原人”微信公众号获取更多校招动态 |
请直接扫描下方二维码获取具体校招行程
根据需求选择校招站点报名参加宣讲会 |
|
![]() |
![]() |
站点 | 学校 | 时间 | 地点 |
杭州 | 浙江大学 玉泉校区 | 2019年10月25日 18:00 - 21:00 | 曹光彪东楼502会议室 |
上海 | 上海交通大学 闵行校区 | 2019年11月11日 14:00 - 17:00(暂定) | 铁生馆200号报告厅(暂定) |
上海 | 复旦大学 张江校区 | 2019年10月16日 14:00 - 17:00 | 食堂三楼小报告厅 |
武汉 | 华中科技大学 | 2019年9月26日 18:30 - 21:30 | 光电学院南五楼613室 |
南京 | 东南大学 九龙湖校区 | 2019年9月20日 14:00 - 17:00 | 大学生活动中心一楼圆形报告厅 |
合肥 | 合肥工业大学 翡翠湖校区 | 2019年9月10号 13:00 - 16:00 | 综合楼302 |
成都 | 电子科技大学 清水河校区 | 2019年9月6日 14:00 - 17:00 | 图书馆二楼求实厅(原600人报告厅) |
西安 | 西安电子科技大学 北校区 | 2019年9月3日 14:00 - 17:00 | 阶梯教学楼112室 |
Senior Design Engineer, ZSP Hardware Design
地点: Plano, TexasProcessor core and subsystem microarchitecture and design
Actively participate in design, architecture and verification reviews
RTL design and synthesis to analyze & optimize power, speed and area of physical implementation
Define, maintain and enhance Block level verification environments using latest flows
Develop and support reusable design and verification infrastructure using scripting tools
Write technical design documents
Self-motivated and able to work with little supervision, must be a good team player
Innovative and passionate about hardware design and excited to take on challenging assignments
Willing to work outside of comfort zone and able to learn and master new designs with minimal support
Strong understanding of processor architectures, instruction set including DSPs – prefer hands-on experience at some level of processor design
Familiarity or experience with cache memory systems, bus interfaces, and peripherals like DMA, I2S, SPI, PDM
Expert in Verilog, SytemVerilog, design compiler, scripting tools (python/perl), verification tools and flows
Experience with ASIC/SOC/FPGA design and verification flows.
Experience or knowledge of physical design implementation flow with Synopsys tools.
Comfortable with programming in C/C++/System C/Assembly
Excellent communication skills (written and spoken English)
Senior Software Engineer, ZSP Software Development Tools
地点: Plano, TexasEnhance and Maintain Compiler for a range of DSP cores
Work on scheduler and optimizer for improving performance and code density of compiler generated code
Port GNU compiler sources to MCU+DSP, and vector DSP processors
Work with Application developers and Hardware engineers to debug code generation bugs and identify any deficiencies or optimization opportunities
Work with a geographically distributed team in building and verifying the entire tool chain
Assist field engineers in supporting customers with tools issues
Self-motivated and able to work with little supervision, Team player
Innovative and passionate about coding and excited to take on challenging assignments
Expert in C/C++ programming with ability to learn and master new C projects with minimal support
Good understanding of processor architecture and instruction set including DSPs
Comfortable with Linux and Windows environments
Excellent communication skills (written and spoken English)
Experience working with GNU C/C++ or any other compiler sources
Willing to work on tools projects outside of compiler (eg. debugger, assembler, linker)
Education: Master's degree or higher in Computer Science/Math with 5+ years experience in embedded software tools design.
Sr. ASIC Design Engineer
地点: San Jose, CASolid front-end RTL design with complex ASIC design experience
Knowledge or experience of GPU/CPU or video/display architecture and design is plus
take the ideas/concepts to algorithms, u-arch, design implementation and chip production
BSEE with 5+ year experience
Staff Application Engineer
地点: San Jose, CADevelop expert level understanding of IP product offerings and the applications, and define new feature or product specification based on in-depth understanding of customer requirements
Engage with customer in technical evaluation, provide respond to technical requests or questions, and managing the engagement
Maintain good customer relationship, support and resolve their issues, identify needs and new opportunities
Perform technical training, presentation, and demo to customers, sales, and engineers
Working with sales and customers in technical evaluation and managing the engagement progress
Maintain good customer relationship, support and resolve their issues, identify needs and new opportunities
6+ years hands-on experience in application or product engineering in the relevant semiconductor area
Experience in customer interface or support
Familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation)
Working experience in one of the fields in video, image processing, graphics, multi-media, computer vision, or neural network
Skillful in analysis, generate ideas, and provide innovative solutions to solve technical problems
Self-motivated, team work, and good communication skills in English
GPU Architecture Engineer
地点: San Jose, CADesign and implement new features in GPU architecture and C-Model.
Maintain existing GPU architecture and C-Model.
Evaluate and improve performance and quality of GPU architecture.
Design interface with driver.
Work with RTL team on hardware verification.
Work with driver team on software integration.
BS in Computer Science or Electircal Engineering.
3 years experience in related position.
Experience in GPU architecture and C-Model is a plus.
Machine learning/Computer Vision Architect
地点: San Jose, CAUnderstand and analyze state of the art machine learning and computer vision algorithms.
Help develop architecture models and setup testing flow to verify.
Help build product prototypes and differentiate solutions.
Help identify performance bottlenecks and optimize HW/SW implementations.
Help perform experiments and enhance tool flows based on popular frameworks.
BS/MS/PhD degree in EE, CS or equivalent.
Familiar with C/C++, Python, and Linux.
Knowledge of machine learning, computer vision, and computer architecture.
Hands-on experiences with TensorFlow, Caffe, benchmark CNN Models.
Analytic and problem-solving skills.
Team player and self-motivated.
3+ years of related industry experiences
Experiences with Voice Recognition and Natural Language Processing.
Experiences with GPU/DSP/ISP/SoCs architecture or system software.
Experiences with OpenCL, OpenVX, CUDA, OpenCV or OpenGL/DirectX.
Sr. Engineer of Analog SerDes PHY Design
地点: ShanghaiDevelop challenging analog circuits independently, including circuit design, simulation, testing, debugging and improvement.
Determine system requirement, define project specifications according to customer’s requirement.
Lead the project development.
Contribute phenomenally to problem solving in circuit design, testing and debugging.
Supervise layout development.
Provide technical support for Customer/FAE/Sales.
Master degree or above in EE.
With 2+ years of work experience in analog and SerDes design.
Experience with the architecture design and production of LVDS RX/TX ,HDMI RX/TX,or DP RX/TX.
Experience with PLL, CDR, RX, TX or Equalizer design in deep-submicron CMOS.
Experience with SerDes PHY circuit design.
Experience with USB3.0, HDMI, MIPI, Display Port and PCI Express Transceiver.
Fluent in both English and Chinese.
Self motivated, good communication skill and team work spirit.
Senior/Staff Engineer of IO Design
地点: ShanghaiDesign General IO library and Customization IO library, provide instruction on layout work.
Design ESD cell and provide ESD guideline for different foundry and process node.
Provide whole chip ESD solution and pad cell floor plan on chip design.
ESD/LU test and Failure Analysis if chip has reliability issue.
M.S. in EE or equivalent.
Knowledge in process , device, physical layout.
Experience on timing model and IBIS model.
Experience on DDR/SD/eMMC/LVDS IO is better.
Good communication skills and good team work spirit.
RF IC Design Engineer
地点: Shanghai基于CMOS工艺的射频收发芯片的电路和系统设计,制定各模块性能指标和实现方案;
独立进行射频电路模块的设计,其中包括电路结构的确立、行为级和电路级的仿真、电路的实现和芯片的测试,并指导系统级射频应用。
模拟和射频集成电路设计相关的硕士以上学历。
至少有一年以上射频或者模拟集成电路设计经验,有成功的芯片投片及产品量产经验。
掌握模拟集成电路设计相关专业知识,具有较强模拟集成电路分析设计能力。
掌握无线通信技术等相关专业的知识,掌握射频集成电路的设计流程,射频电路理论及分析能力较强,具有扎实的电磁场微波理论基础。
熟悉射频收发电路的基本结构,掌握基本模拟和射频电路单元,熟悉射频主要器件,能够独立完成射频部分电路原理设计、建模、仿真、测试和调试等相关工作,能够指导进行RF布线;有AD/DA, PLL,PA,LNA,MIXER,Filter,VGA 电路设计经验尤佳。
掌握常用射频测试仪器,如网络分析仪,频谱分析仪,信号发生器等;掌握射频电路的测试方法。
熟悉EDA软件,Cadence Spectre,ADS,HFSS等。
具有创新能力、良好的沟通能力和团队精神。
System Administrator
地点: ShanghaiTroubleshoot and administer engineering systems which are built up by Unix/Linux/Solaris systems.
Troubleshoot and manage network structure, it covers WAN, LAN, VPN.
Daily monitor system running status, system performance.
Make regular tape backup and plan recovery test.
Work with team members to optimize network and systems.
Bachelor of Computer science or related subjects, over 4 years of System Administrator experience.
In-depth knowledge of Unix/Linux systems, TCP/IP and network security, have rich experiences on NIS, NFS, SAN and NAS storage.
Experience with scripting for Solaris and Linux based OS.
Experience with virtualization technologies (VMware ESX/ESXi), NetApp management is preferred.
Strong capability and awareness of leaning new technologies.
Self-motivated and team spirit.
Fluent in English reading and writing. Experience in multinational company is preferred.
Manager of Product Engineering
地点: ShanghaiManage local team of product and application engineers.
Develop expert level understanding of IP product offerings, and define new feature or product specification based on in-depth understanding of customer requirements.
Working with sales and customers in technical evaluation and managing the engagement.
Maintain good customer relationship, support and resolve their issues, identify needs and new opportunities.
Perform technical training, presentation, and demo to customers, sales, and engineers.
6+ years hands-on experience in product or application engineering in the relevant semiconductor area, experience in managing a team is a plus.
Familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation).
Working experience in one of the fields in graphics, video, multi-media, image processing or computer vision.
Skillful in analysis, generate ideas, and provide innovative solutions to solve technical problems.
Self-motivated, team work, and good communication skills in English.
Staff Engineer of Product Engineering
地点: ShanghaiDevelop expert level understanding of IP product offerings, including capabilities, competitiveness, and the applications.
Define new feature or product specification based on in-depth understanding of customer requirements.
Engage with customer in technical evaluation, provide respond to technical requests or questions, and managing the engagement.
Maintain good customer relationship, support and resolve their issues, identify needs and new opportunities.
Perform technical training, presentation, and demo to customers, sales, and engineers.
4+ years hands-on experience in product or application engineering in the relevant semiconductor area.
Familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation).
Working experience in one of the fields in graphics, video, multi-media, image processing or computer vision.
Skillful in analysis, generate ideas, and provide innovative solutions to solve technical problems.
Self-motivated, team work, and good communication skills in English.
Senior/Staff Engineer of Video IP Design
地点: ShanghaiPlay an important role in defining video IP spec and devising Video IP architecture.
Develop challenging modules including module spec definition, macro architecture design, RTL coding, C coding, simulation and synthesis.
Carry out IP level verification or IP blocks integration/implementation.
Help junior engineers to solve technical issues.
Support customers regarding Video IP application.
Bachelor degree or above in EE.
5+ years of work experience in related areas.
Good knowledge of some of the following general IP: H.264, H.265, MPEG, JPEG, AVS, AVS+ decoder & encoder and so on.
Skilled in the field of digital circuit design, whole digital design flow and EDA tools.
Skilled in some of the following disciplines: RTL coding, C coding, Catapult C coding, simulation, synthesis/DFT/STA. Knowledge about catapult C design flow is a plus.
Key member in at least one mature silicon proven video IP.
Fluent in both English and Chinese.
Self motivated, good communication skill and team work spirit.
Project Leader of Video IP Design
地点: ShanghaiPlay a leadership role in defining video IP spec and devising Video IP architecture.
Develop challenging modules including module spec definition, macro architecture design, RTL coding, C coding, simulation and synthesis.
Carry out IP level verification or IP blocks integration/implementation.
Be responsible for project progress control and design schedule.
Help engineers to solve technical issues.
Support customers regarding Video IP application.
Bachelor degree or above in EE.
7+ years of work experience in related areas.
Good knowledge of some of the following general IP: H.264, H.265, MPEG, JPEG, AVS, AVS+ decoder & encoder and so on.
Skilled in the field of digital circuit design, whole digital design flow and EDA tools.
Skilled in some of the following disciplines: RTL coding, C coding, Catapult C coding, simulation, synthesis/DFT/STA. Knowledge about catapult C design flow is a plus.
Leader at least one mature silicon proven video IP.
Fluent in both English and Chinese.
Good customer communication skill.
Self motivated, good communication skill and team work spirit.
Engineer of GPU & Vision Architecture
地点: ShanghaiGPU & Vision architectural modeling and analysis of graphics/compute/vision algorithms and features.
Document/design/develop tools to validate models and analyze performance.
Develop tests, test plans, and testing infrastructure for new graphics/compute/vision architectures/features.
Co-work with RTL team, cross-validate model and RTL.
Master or PHD degree in Graphics, CS, EE, or Math.
Strong C/C++ programming skills, perf/python programming skills is a plus.
Excellent in mathematics or solid understanding of graphics pipeline (such as DX/OpenGL)/compute (such as openCL/Cuda/DX Compute) / Vision (such as OpenVX/DL/NN/TensorFlow).
Strong background in computer architecture is a good plus.
Experience in upstream industry (such as game-engine/modeling for algorithm of parallel computation/HPC/vision applications) is good plus.
Experience in performance analysis for GPU and vision processor is a big plus.
Good written and spoken English.
Self motivated, team work, and good communication are a must.
Engineer of Compiler Software
地点: ShanghaiCapable of independently contributing to and working on the design/implementation/verification of passes of certain intermediate-language representation level of backend compiler for GPU/DSP targets.
Capable of designing/implementing optimization algorithm for our world-class optimizing compiler.
Work closely with driver engineers/hardware architecture engineers/tool engineers to solve functional verification and performance tuning.
Work closely with QA/PM team to solve software release/customer issues under pressure.
Experience with compiler development in academia or industry environment.
Knowledge of modern compiler technologies, including intermediate-language representation, platform dependent/independent optimizations, functional transformation, code generation, etc.
Knowledge of compiler-related data structures and algorithms such as graph algorithms, analysis and optimization algorithms.
Familiarity with graphics shading languages, LLVM and GPU architectures a definite plus.
Experience of working with a large code base with C/C++, assembly programing language.
MS or PhD in Computer Science or Computer Engineering.
Senior/Staff ASIC Design Engineer of AR/AI Project
地点: ShanghaiDesign top-of-the-line graphics/Vision processors, including specification, architecture, micro-architecture, implementation (using Verilog), and verification.
3+ years hands-on experience.
Programming skills in Verilog HDL.
Must be familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation).
Highly motivated and skillful at solving difficult technical problems.
Knowledge of computer graphics and low-power design techniques is a plus.
Experience of OpenCL VX is a plus.
Experience of Neural Network and Tensor Processing design is a plus.
Sr. Staff/Staff Engineer of GPU Design
地点: ShanghaiDesign top-of-the-line graphics/Vision processors, including specification, architecture, micro-architecture, implementation (using Verilog), and verification.
3+ years hands-on experience.
Programming skills in Verilog HDL.
Must be familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation).
Highly motivated and skillful at solving difficult technical problems.
Knowledge of computer graphics and low-power design techniques a plus.
Experience of memory controller or AXI bus design is a plus.
Staff Engineer of ISP Design
地点: ShanghaiDesign top-of-the-line image processors, including specification, architecture, micro-architecture, implementation (using Verilog), and verification.
3+ years hands-on experience.
Programming skills in Verilog HDL.
Must be familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation).
Highly motivated and skillful at solving difficult technical problems.
Knowledge of computer graphics and low-power design techniques a plus.
Experience of image process design is a plus.
Sr. Engineer of Circuit Design
地点: ShanghaiDevelop challenging analog circuits independently, including circuit design, simulation, testing, debugging and improvement.
Determine system requirement, define project specifications according to customer’s requirement.
Lead the project development.
Contribute phenomenally to problem solving in circuit design, testing and debugging.
Supervise layout development.
Provide technical support for Customer/FAE/Sales.
Master degree or above in EE.
With 2+ years of work experience in the analog circuit related areas.
Good knowledge in at least one of the following disciplines: VCO, PLL, DLL, PCIex, USB, SATA, LVDS, HDMI, etc.
Experience on high speed SerDes architecture or circuit is a plus.
Good understanding about the entire development flow of IC design, including process, package, testing, etc.
Fluent in both English and Chinese.
Self motivated, good communication skill and team work spirit.
Engineer/Sr. Engineer of System Application
地点: ShanghaiDesign and develop Embedded System in ASIC and SoC projects, including design and debug hardware and firmware like BSP, Drivers and API on board level.
Carry out System/Sub-system/IP FPGA verification/validation for IC and SoC design.
Perform in house test for IC and SoC products.
Work with project members to determine system requirement, design prototyping and support customers in product applications; Play an important role in SoC and System project development.
Provide technical support for Customer/FAE/Sales.
Bachelor degree or above in EE, CS or Automation.
2+ years of work experience in the related areas.
Track record of successfully silicon proven System or SoC projects.
Good architecture knowledge about at least 2 types of the following SoC systems: ZSP/ARM/8051/Power PC and peripheral systems.
Good knowledge/experience in ZSP/8051/ARM embedded system development, including BSP, Device Driver and API development.
Clear understanding of hardware/software interaction and system level tradeoffs.
Good knowledge/experience in C/C++ and ASM; FPGA/ASIC prototyping/demo system design, development, synthesis and application reuse; debugging board, firmware and FPGA, etc. on system level.
Familiar with lab equipment.
Fluent in both English and Chinese.
Self motivated, good communication skill and team work spirit.
Engineer/Sr. Engineer of Embedded Software
地点: ShanghaiPort Embedded Linux/Android for SoC chip, develop Linux driver and API for application.
Work with project members to determine system requirement, design prototyping and support customers in product applications.
BSEE/CS 3+ years embedded software development experience in Linux.
Good knowledge/experience in ARM/PowerPC embedded system development, PowerPC/ARM processor architecture and PowerPC/ARM Compiler.
Experienced in the drivers of CPU peripheral like LCD, NAND, flash, I2C, SPI, etc.
Experienced in embedded system design.
Working knowledge of the GNU tool chain for software development.
Android development experience and hardware related knowledge will be a plus.
Strong problem solving and analytical skills.
Self-motivated and good team player.
Good written and spoken English.
Engineer/Sr. Engineer of SoC FE Flow
地点: ShanghaiComprehend the SoC clock structure and working mode and prepare the SDC file for SoC design.
Prepare the DFT plan for the SoC design.
SCAN/MBIST/BSD insertion and synthesize methodology for Flatten / Hierarchical design.
Pre/Post simulation for test patterns.
Cooperate with timing engineer for timing signoff (STA).
Analog IP test implementation and simulation.
Support ATE engineer for chip testing debug, and analyze ATE log file to locate root cause of failure.
Formal check of RTL and netlist.
Bachelor's degree or above, major in EE, CS or relevant.
Above 5years work experience to the one with Bachelor's degree and above 3years with Master's degree is required for Senior Engineer position.
Skilled in SoC PPA, better for low power design.
Improve low test coverage to achieve higher coverage.
Skilled in csh/perl/tcl scripts.
Be familiar with concept of SoC and P&R physical implementation.
Fluent in both English and Chinese.
Good team work spirit.
Sr. Engineer/Staff Engineer of SoC Verification
地点: ShanghaiUnderstanding the expected functionality of designs.
Developing testing and regression plans.
Designing and developing verification environment.
Running RTL and gate-level simulations/regression.
Code/functional coverage development, analysis and closure.
Minimum of 3 years design/verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
Knowledge in ASIC/FPGA design process and verification tools/env ( UVM/OVM…).
Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
Scripting and automation skills (tcl, perl, makefile etc) a plus.
Familiar with C/C++.
Knowledge of DDR/Video/ARM/USB/PCIE , Low Power Verification with UPF and design experience is a plus.
Experience in CPU/DSP verification, including test plan and test bench development, test case development and test coverage assessment. and Knowledge of computer architecture and micro-architecture (pipeline, out-of-order, cache) is a plus.
Additional qualifications include: Good IC verification skills and basic knowledge of logic or circuit design, good communication and problem solving skills.
Independent and self-managing.
Engineer/Sr. Engineer of SoC Design
地点: ShanghaiPlay an important role in defining chip spec and devising chip architecture.
Develop challenging modules including module spec definition, macro architecture design, RTL coding, simulation and synthesis.
Carry out chip level verification or chip integration/implementation.
Help junior engineers to solve technical issues.
Support customers regarding chip applications.
Bachelor degree or above in EE, 3+ years experience.
Good knowledge of some of the following general IP: CPU/DSP, AMBA, DDR/SDRAM, video (HEVC, MIPI…), parallel/serial peripheral module, DMA, interrupt, timer, GPIO.
Good skill in the field of digital circuit design, whole digital design flow and EDA tools;
Key member in at least one successfully silicon proven challenging project.
Fluent in both English and Chinese.
Self motivated, good communication skill and team work spirit.
Engineer/Sr. Engineer of Design Implementation
地点: ShanghaiResponsible for SDC and UPF/CPF development and debug.
Focus on design floor planning, power planning, IO planning, placement & CTS and routing, handling timing and congestion issue during project implementation.
IP level and chip level physical verification and DFM rule checking.
Power analysis and IR drop/EM analysis for both static and dynamic.
Strong capability in timing analysis, and independently handle all timing issues from netlist/RTL to GDS process.
Responsible for timing signoff for all functional modes and concerns, and work closely with DFT engineer for scan modes timing closure.
Work closely with package team and IO team regarding IO placement to address IO ESD, SSO and chip power supplement concerns.
Communicate with customer as well as AE or sales.
Bachelor’s degree or above in EE.
Skilled in csh/perl/tcl.
2+ years work experience in relevant areas is required for Senior Engineer position.
Good knowledge in at least one of the following disciplines: high speed chip P&R skills, advance node chip P&R, hierarchical flow or low power P&R implementation, physical layout & verification.
Rich experience on timing/noise violation fixing and CTS tree synthesis.
Good understanding about entire development flow of IC design.
Good understanding about FE design, process, package, testing, etc.
Fluent in both English and Chinese.
Self motivated, good communication skill and team work spirit.
Manager of Program Management
地点: ChengduEngage with customers to monitor customers’ project execution and make sure requirements, deliverables and schedule are being met.
Work with cross-functional teams in our division to address customers’ issues or questions and provide resolution.
Coordinate regular meeting with customers and internal teams as needed to track status and monitor progress.
Prepare status and progress reports on regular basis to check against plan-of-record.
Gathering customers’ feedback and understand their pain-points to back propagate internally for improvement.
Proven experience in high-tech industry related program management.
Excellent organizational and communication skills.
Having ability and will to work positively with a wide range of customers and individuals.
Strong understanding of project and program management methodologies and techniques.
Good knowledge of scheduling and resource allocation procedures.
Software Release Qualification Engineer
地点: ChengduGood understanding the functionality of products and related knowledge.
Follow the arrangement to finish assigned tasks on schedule with good quality independently.
Automate product test cases using Python, and execute product testing.
File bugs in Bugzilla, track bug process and communicate with co-work to solve product issues.
Summarize the test reports.
Bachelor or Master degree on Electrical, Computer, Automation or related majors.
Familiar to at least one of C/C++.
Familiar to at least one scripting language, such as bash, python, perl, php.
Familiar to Linux system, familiar to code compilation on Linux.
Experience in graph and image processing is a plus.
Experience in video codec is a plus.
Experience in automation testing is a plus.
Independent and good self-managing.
Good communication and problem solving skills, and good team player.
Good English on reading and writing.
At leave one year software testing experience.
ISP Driver Staff Engineer
地点: ChengduThe ideal candidate will be extremely passionate for ISP and Sensor driver design. He or she will be part of the talented ISP team to build up the high quality platform of VeriSilicon ISP products, and driving up the easy-using capability and performance of the ISP platform.
Develop driver for Sensor, bring up CMOS sensors as well as initialization.
Develop driver for ISP products.
Validate functionality of ISP pipeline on FPGA.
Co-work with customer to launch ISP integrated platform.
Bachelor or above degree in electronics engineering, computer science, image signal process related fields, 2+years ISP driver development.
Excellent C/C++ language and Linux, RTOS, OS-less, V4L2 understanding.
Familiar with ISP pipeline and image-forming principle of CMOS sensor in OmniVision, ONSEMI and SONY, understand sensor interface such as DVP, MIPI, LVDS and so on.
Knowledge on camera 3A algorithm (AE, AWB, AF).
Experience with image quality evaluation and tuning.
Experience with CMOS sensor driver and bring up.
Understand MATLAB language is a good plus.
Understand IQ tradeoffs of different ISP blocks is a good plus.
Excellent interpersonal communication skills, good team spirit and adaptability.
Open minded and fast learning.
Software Engineer
地点: ChengduAs a software engineer, you will work on software development projects for Computer Vision and ML accelerator from middleware and application and performance analysis. You will also work with hardware design team together to verify and test the IP. Helping out customers to integrate our IPs and support their production is also one of the responsibilities.
2+ year software development experiences.
Good C programming skill.
Understand basic concepts in operation system and data structure/algorithm.
Experience with large software code bases is a plus.
Experience in any projects related is a plus.
Experience in Python programming is a plus.
Good written and spoken English.
Multimedia Video Codec SW Engineer
地点: ChengduVideo codec control SW module design, multimedia video playback SW development.
Linux kernel driver implementation for HW video codec.
Customer project for special requirements/features in schedule.
Customer service on technical support and reported bugs fix.
MS, PHD in SE, CS, EE or related IT technology fields.
Understanding of Android/Linux multimedia frame work, Stagefright, Gstreamer, FFMPEG, OMXIL/Codec2.0 or V4L2; good in C/C++ design, better on embedded software field.
Some knowledge on Linux kernel development.
Some knowledge on video formats (H264/HEVC/MPEG2...) stream syntax, or video stream file container.
Good Mandarin and English communication skills.
Good team work and passion in high pressure.
System Software Engineer
地点: ChengduBe responsible for the development and maintenance of embedded system driver, based on ARM/PPC/x86 architecture.
Be responsible for driver code integration for Android, Linux window system.
Cooperate with other departments to complete the project and provide the required driver development and software testing support.
Bachelor degree or above, major in Computer, Communication, Electronics.
Familiar with Linux-based software development and debugging methods.
Familiar with C/C++ programming. Java is a plus.
Able to read and understand English data manuals and technical documents.
Knowledge of Computer Graphics(Opengl, OpenglES .etc) is a plus.
Strong sense of responsibility, good practical ability, independent analysis and problem solving ability.
2D Software Development Engineer
地点: ChengduBe responsible for the development and maintenance of embedded system driver, based on ARM/PPC/x86 architecture.
Be responsible for Display Controller, 2D graphics GPU, Vector Graphics GPU driver development and integration and debug.
Cooperate with other departments to complete the project and provide the required software testing support.
Bachelor degree or above, major in Computer, Communication, Electronics.
Familiar with Linux-based software development and debugging methods; Proficiency in C program language is required.
Able to read and understand English data manuals and technical documents.
Being familiar with DFB/DRM/KMS (Direct FB/Direct Rendering Manger/Kernel Mode Setting) framework is preferred.
Practical, strong sense of responsibility, good practical ability, independent analysis and problem solving ability.
Software Engineer (Driver)
地点: ChengduGPU software (CD) team delicately focus on developing GPU 3D graphics and OpenCL computing driver. Overall, there are very few engineers in China who are really deeply involved in 3D graphics core technology. This team is one of them. Here you can learn the latest progress on 3D software API and the detail of graphics architecture design. Of course, you also can learn how a real 3D graphics driver looks like, how the driver works with hardware and helps upper level applications to present a nice and smooth user experience.
Good C programming skill.
Understand basic concepts in operation system and data structure/algorithm.
Experience with large software code bases.
Be interested in GPU and good learning skills.
Background in 3D model/render, computer graphics, game engine, etc, would be preferred.
Engineer/Sr. Engineer of ZSP System Software
地点: ChengduAs a software engineer, you will work on software development projects for Verisilicon audio DSP(ZSP) related algorithm and software, including audio codec, audio signal processing, performance optimization on audio DSP(ZSP), ASR, and related profiling/testing work.
Master degree or above in EE/CS or computer science related major.
Solid C programming skill.
Understand basic concepts in audio processing and data structure/algorithm.
Good written and spoken English.
Good communication skills and team player.
Experience with audio algorithm/audio processing is a plus.
Experience in ARM/DSP algorithm performance optimization is a plus.
Senior/Staff Engineer of VPU Design
地点: ChengduPlay an important role in defining video IP spec and devising Video IP architecture.
Develop challenging modules including module spec definition, macro architecture design, RTL coding, C coding, simulation and synthesis.
Carry out IP level verification or IP blocks integration/implementation.
Help junior engineers to solve technical issues.
Support customers regarding Video IP application.
Bachelor degree or above in EE.
5+ years of work experience in related areas.
Good knowledge of some of the following general IP: H.264, H.265, MPEG, JPEG, AVS, AVS+ decoder & encoder and so on.
Skilled in the field of digital circuit design, whole digital design flow and EDA tools.
Skilled in some of the following disciplines: RTL coding, C coding, Catapult C coding, simulation, synthesis/DFT/STA. Knowledge about catapult C design flow is a plus.
Key member in at least one mature silicon proven video IP.
Fluent in both English and Chinese.
Self motivated, good communication skill and team work spirit.
Staff IP Solution Engineer
地点: ChengduDevelop expert level understanding of IP product offerings, including capabilities, competitiveness, and the applications.
Define new feature or product specification based on in-depth understanding of customer requirements.
Engage with customer in technical evaluation, provide respond to technical requests or questions, and managing the engagement.
Maintain good customer relationship, support and resolve their issues, identify needs and new opportunities.
Perform technical training, presentation, and demo to customers, sales, and engineers.
4+ years hands-on experience in product or application engineering in the relevant semiconductor area.
Familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation).
Working experience in one of the fields in graphics, video, multi-media, image processing or computer vision.
Skillful in analysis, generate ideas, and provide innovative solutions to solve technical problems.
Self-motivated, team work, and good communication skills in English.
Engineer/Sr. Engineer of ZSP Design Verification
地点: ChengduDevelop environments for ZSP system functional verification.
Write verification plans for ZSP system level IPs and systems.
Develop verification environments for IP and systems using C, verilog, Assembly, SystemVerilog, etc.
Contribute improvements to verification methodologies, and toolsets.
Develop script for verification flow with Python, Perl, etc.
3-8 years working experience. BS/MS/PhD in Electrical/Computer Engineering.
Strong coding skills - using languages: Verilog, SystemVerilog, Perl, assembly, C++, C, Linux.
Great debugging and problem isolation skills.
AXI, AHB interconnect.
Computer architecture, memory subsystems.
Implementing verification methodologies including constrained random verification, coverage closure, Assertion Based Verification, Universal Verification Methodology.
Background knowledge for DSP, CPU, Cache is better.
RF Circuit Design Engineer
地点: ChengduDevise and develop deep sub-micron CMOS analog circuit.
Guide and/or supervise layout.
Assist in the design of test boards so as to debug and verify test chips.
MS/PHD degree, majored in EE.
Course knowledge and project experience in the related areas.
Have experience on one or some of the following disciplines: LNA, MIXER, TIA, VCO, PLL, LPF & VGA, PA, other RF blocks.
Self motivated, good communication and team work skills are a must.
Senior/Staff Verification Engineer
地点: ChengduFocus on analog/digital mixed IP and Chip verification. The engineers need to act as a strong team member and contributor, who also need to collaborate with digital F.E team closely.
Understanding the expected functionality of designs.
Developing testing and regression plans.
Designing and developing verification environment.
Running RTL and gate-level simulations/regression.
Code/functional coverage development, analysis and closure.
Minimum of 3 years design/verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
Knowledge in ASIC/FPGA design process and verification tools/env (UVM/OVM…).
Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
Scripting and automation skills (tcl, perl, makefile etc) is a plus; Familiar with C/C++ is a plus.
Knowledge of USB/PCIE/MIPI, ARM based SOC and design experience is a plus.
Additional qualifications include: Good IC verification skills and basic knowledge of logic or circuit design, good communication and problem solving skills.
Independent and self-managing.
Senior/Staff Digital Design Engineer
地点: ChengduFocus on analog/digital mixed IP and Chip design&implementation. The engineers need to act as a strong team member and contributor, who also need to collaborate with analog team and backend team.
Define IP block spec and micro-architecture.
Be in charge of RTL-coding, simulation, synthesis and related F.E flow, support B.E to closure, and support silicon debugging.
Be in charge of subsys or chip integration and implementation.
Analyze and Optimize for PPA.
BS with 4+ years, MS with 3+ years of experience in ASIC or FPGA design.
Good skill in the field of digital logic design, whole digital design flow, especially lint/cdc/synthesis/sta/formal check.
Good knowledge of some general high speed interface IPs is preferred: USB, PCIE, MIPI, etc.
Scripting and automation skill (tcl, perl, makefile, python etc) is a plus.
Individual contributor in 3+ design projects with successful completion.
Self motivated, good communication skill and team work spirit.
Fluent in both English and Chinese.
Senior DFT(Design for Test) Engineer
地点: ChengduComplete DFT test plan definition.
Complete DFT logic design, including: memory BIST, memory BISR, scan insertion, boundary scan insertion, macro testing.
Complete DFT test pattern verification.
Complete DFT mode timing constraint, support DFT mode timing closure.
Support chip bring-up, complete test pattern debugging, yield improvement.
Provide technical support for customer/FAE/sales.
Master of EE, 2+ years DFT work experiences or Bachelor of EE, 5+ years DFT work experiences.
Have following experiences: test plan definition, memory BIST, memory BISR, scan insertion, boundary scan insertion, macro testing logic design and verification, analyze ATE test pattern failure and perform diagnose.
Have back-end Synthesis, P&R, STA experiences is a plus.
Be able to skillfully use the Mentor/Synopsys DFT EDA tools.
Full of enterprise and the spirit of teamwork, good ability to communicate and express, fluent in Mandarin and English.
Senior / Embedded Software Engineer
地点: ChengduDevelop SW driver for peripheral IPs of SOC.
Co-work with ASIC IP team to finish the SOC peripheral IPs related SW verification.
Bachelor degree or above in EE, CS or Automation.
Minimum 3 years of experience in embedded software development.
Familiar with ARM architecture.
Experience in embedded Linux kernel device driver development.
Experience in arm bare metal program develop.
Solid experience of USB/MIPI/SD/emmc driver development.
Good team player, responsible, learning ability.
Senior /System Application Engineer - IOT Protocol Software
地点: ChengduTo development BLE/802.15.4/WIFI related stack and protocol software solution.
To design the IOT wireless application solution including hardware debug and software development.
Co-work with team in customer project to develop the IOT wireless related application solution.
Provide technical support for Customer/FAE/Sales.
Bachelor degree or above in EE, CS or Automation.
Good knowledge/experience in short range wireless system such as BLE/802.15.4/WIFI.
Good experience in stack/protocol development of BLE/802.15.4/WIFI.
Good experience in real time OS development and porting.
Good architecture knowledge about at least 1 type of the following SoC systems: ARM, ZSP and peripheral systems.
Self motivated, good communication skill and team work player.
Engineer/Sr. Engineer of SoC Design Verification
地点: ChengduUnderstanding the expected functionality of designs.
Developing testing and regression plans.
Designing and developing verification environment.
Running RTL and gate-level simulations/regression.
Code/functional coverage development, analysis and closure.
Minimum of 3 years design/verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
Knowledge in ASIC/FPGA design process and verification tools/env (UVM/OVM…).
Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
Scripting and automation skills (tcl, perl, makefile etc) a plus.
Familiar with C/C++.
Knowledge of DDR/Video/ARM/USB/PCIE, Low Power Verification with UPF and design experience is a plus.
Experience in CPU/DSP verification, including test plan and test bench development, test case development and test coverage assessment, and knowledge of computer architecture and micro-architecture (pipeline, out-of-order, cache) is a plus.
Additional qualifications include: Good IC verification skills and basic knowledge of logic or circuit design, good communication and problem solving skills.
Independent and self-managing.
Engineer/Sr. Engineer of SoC Design
地点: ChengduPlay an important role in defining chip spec and devising chip architecture.
Develop challenging modules including module spec definition, macro architecture design, RTL coding, simulation and synthesis.
Carry out chip level verification or chip integration/implementation.
Help junior engineers to solve technical issues.
Support customers regarding chip applications.
Bachelor degree or above in EE, 3+ years experience.
Good knowledge of some of the following general IP: CPU/DSP, AMBA, DDR/SDRAM, Video (HEVC, MIPI…), parallel/serial peripheral module, DMA, interrupt, timer, GPIO.
Good skill in the field of digital circuit design, whole digital design flow and EDA tools.
Key member in at least one successfully silicon proven challenging project.
Fluent in both English and Chinese.
Self motivated, good communication skill and team work spirit.
通过订阅电子邮件接收最新的芯原新闻