• 负责ASIC/SOC和IP子系统的软件开发项目，从驱动软件到中间件，以及应用级软件和性能分析

• 与硬件设计团队一起验证和测试系统/子系统/IP验证

• 帮助客户整合软件解决方案并支持其量产

• CS、EE或相关专业，本科以上学历

• 有良好的C/C++编程能力

• 对操作系统和数据结构/算法有很好的理解 

• 良好的问题解决和设计文档技能，自我激励，良好的沟通能力和团队合作精神

• 良好的英语听说读写能力

以下为加分项：

• 在嵌入式系统开发方面具有良好的知识/经验，包括BSP、设备驱动程序和API开发

• 清楚了解硬件/软件交互和系统级性能分析

• 熟悉实验室设备的使用，如数字示波器、逻辑分析仪

VeriSilicon is seeking an experienced Sr Director of ASIC Design to join our high-performing team.

• Leads ASIC design team to develop and productize next generation SoC’s 

• Work with cross-functional project teams to define product specifications, system architecture, HW/SW partitioning, and execution plan

• Implement best SoC development practices, improving design methodology to maximize efficiency and predictability

• Deliver chip architecture, design, integration, programming model, verification, and manages hand-off to backend

• Validate silicon, support system integration, and production testing

• Drive innovation, proving leadership to the organization to ensure world-class system solutions and flawless execution

• Manage team, hire and retain best talent

Proven track record of success in high-performance/high-volume semiconductor markets and desired experience in following areas:

• SoC, embedded CPU and bus architectures, Media; Graphics, Video encode, decode, Audio. Networking and control interfaces, machine leaning and AI.

• Communications/DSP algorithms and power/area efficient implementations

• Digital IC design, design for low power and high speed, design for test (DFT)

• System modeling, RTL coding, Lint/CDC checking, simulation, synthesis, power analysis, timing analysis in Cadence/Synopsys design environments

• Directed and constrained random verification, UVM methodology

• Embedded systems FPGA emulation, lab debug and chip validation

• Project planning and execution, and performing design tradeoffs to achieve performance, power, die size, and schedule targets

• Self-motivated, excellent communication skills, and ability to excel and to provide leadership in a fast paced environment

• MS + 15 years’ experience, experience, including 5+ years in a senior management role

• Design and implement new features in GPU architecture and C-Model.

• Maintain existing GPU architecture and C-Model.

• Evaluate and improve performance and quality of GPU architecture.

• Design interface with driver.

• Work with RTL team on hardware verification.

• Work with driver team on software integration.

• BS in Computer Science or Electrical Engineering.

• 1-year experience in related position.

• Experience in GPU architecture and C-Model is a plus.

• Develop expert level understanding of digital IP applications in the fields of artificial intelligence, computer vision, video processing, imaging, and computer graphics.

• Collaborate internally and externally with R&D developers and customers to define new product features and specification based on in-depth understanding of customer or market requirements. .

• Engage with customer in technical evaluation or customer project, capture product deficiency or problems to be solved, understand the unique goals of each project, make careful assessment, and managing the engagement progress.

• Perform technical training, presentation, and demo to customers, events, sales, and engineers.

• Develop applications as needed to improve existing software, provide solution and technical support on-site.

• Maintain good customer relationship, support and resolve their issues, identify needs and new opportunities.

• 6+ years hands-on experience in application or product engineering in the relevant semiconductor area.

• Experience in customer interface or support.

• Familiar with software development, architecture and components.

• Working experience in one of the fields in video, image processing, graphics, multi-media, computer vision, neural network or artificial intelligence.

• Skillful in analysis, generate ideas, willing to jump in and tackle new challenges, and provide innovative solutions to solve technical problems.

• Proactive, self-motivated, team-work, and effective communication skills in English.

Design top-of-the-line graphics processors, including specification, architecture, micro-architecture, implementation (using Verilog), and verification.

• 5+ years hands-on experience with focus on front-end complex RTL design.

• Programming skills in Verilog.

• Must be familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation).

• Highly motivated and skillful at solving difficult technical problems.

• Knowledge of computer graphics and low-power design techniques a plus.

• Experience of GPU shader design a plus.

• Processor core and subsystem microarchitecture and design
  

• Actively participate in design, architecture and verification reviews
  

• RTL design and synthesis to analyze & optimize power, speed and area of physical implementation

• Define, maintain and enhance Block level verification environments using latest flows

• Develop and support reusable design and verification infrastructure using scripting tools

• Write technical design documents

• Self-motivated and able to work with little supervision, must be a good team player
  

• Innovative and passionate about hardware design and excited to take on challenging assignments

• Willing to work outside of comfort zone and able to learn and master new designs with minimal support

• Strong understanding of processor architectures, instruction set including DSPs – prefer hands-on experience at some level of processor design

• Familiarity or experience with cache memory systems, bus interfaces, and peripherals like DMA, I2S, SPI, PDM

• Expert in Verilog, SytemVerilog, design compiler, scripting tools (python/perl), verification tools and flows

• Experience with ASIC/SOC/FPGA design and verification flows.

• Experience or knowledge of physical design implementation flow with Synopsys tools.

• Comfortable with programming in C/C++/System C/Assembly

• Excellent communication skills (written and spoken English)

• Enhance and Maintain Compiler for a range of DSP cores

• Work on scheduler and optimizer for improving performance and code density of compiler generated code

• Port GNU compiler sources to MCU+DSP, and vector DSP processors

• Work with Application developers and Hardware engineers to debug code generation bugs and identify any deficiencies or optimization opportunities

• Work with a geographically distributed team in building and verifying the entire tool chain

• Assist field engineers in supporting customers with tools issues

• Self-motivated and able to work with little supervision, Team player

• Innovative and passionate about coding and excited to take on challenging assignments

• Expert in C/C++ programming with ability to learn and master new C projects with minimal support

• Good understanding of processor architecture and instruction set including DSPs

• Comfortable with Linux and Windows environments

• Excellent communication skills (written and spoken English)

• Experience working with GNU C/C++ or any other compiler sources

• Willing to work on tools projects outside of compiler (eg. debugger, assembler, linker)
  

• Education: Master's degree or higher in Computer Science/Math with 5+ years experience in embedded software tools design.
  

• Understand and analyze state of the art machine learning and computer vision algorithms.

• Help develop architecture models and setup testing flow to verify.

• Help build product prototypes and differentiate solutions.

• Help identify performance bottlenecks and optimize HW/SW implementations.

• Help perform experiments and enhance tool flows based on popular frameworks.

• BS/MS/PhD degree in EE, CS or equivalent.

• Familiar with C/C++, Python, and Linux.

• Knowledge of machine learning, computer vision, and computer architecture.

• Hands-on experiences with TensorFlow, Caffe, benchmark CNN Models.

• Analytic and problem-solving skills.

• Team player and self-motivated.

• 3+ years of related industry experiences

• Experiences with Voice Recognition and Natural Language Processing.

• Experiences with GPU/DSP/ISP/SoCs architecture or system software.

• Experiences with OpenCL, OpenVX, CUDA, OpenCV or OpenGL/DirectX.

• Develop challenging analog circuits independently, including circuit design, simulation, testing, debugging and improvement.

• Determine system requirement, define project specifications according to customer’s requirement.

• Lead the project development.

• Contribute phenomenally to problem solving in circuit design, testing and debugging.

• Supervise layout development.

• Provide technical support for Customer/FAE/Sales.

• Master degree or above in EE.

• With 2+ years of work experience in analog and SerDes design.

• Experience with the architecture design and production of LVDS RX/TX ,HDMI RX/TX,or DP RX/TX.

• Experience with PLL, CDR, RX, TX or Equalizer design in deep-submicron CMOS.

• Experience with SerDes PHY circuit design.

• Experience with USB3.0, HDMI, MIPI, Display Port and PCI Express Transceiver.

• Fluent in both English and Chinese.

• Self motivated, good communication skill and team work spirit.

• Design General IO library and Customization IO library, provide instruction on layout work.

• Design ESD cell and provide ESD guideline for different foundry and process node.

• Provide whole chip ESD solution and pad cell floor plan on chip design.

• ESD/LU test and Failure Analysis if chip has reliability issue.

• M.S. in EE or equivalent.

• Knowledge in process , device, physical layout.

• Experience on timing model and IBIS model.

• Experience on DDR/SD/eMMC/LVDS IO is better.

• Good communication skills and good team work spirit.

• 基于CMOS工艺的射频收发芯片的电路和系统设计，制定各模块性能指标和实现方案；

• 独立进行射频电路模块的设计，其中包括电路结构的确立、行为级和电路级的仿真、电路的实现和芯片的测试，并指导系统级射频应用。

• 模拟和射频集成电路设计相关的硕士以上学历。

• 至少有一年以上射频或者模拟集成电路设计经验，有成功的芯片投片及产品量产经验。

• 掌握模拟集成电路设计相关专业知识，具有较强模拟集成电路分析设计能力。

• 掌握无线通信技术等相关专业的知识，掌握射频集成电路的设计流程，射频电路理论及分析能力较强，具有扎实的电磁场微波理论基础。

• 熟悉射频收发电路的基本结构，掌握基本模拟和射频电路单元，熟悉射频主要器件，能够独立完成射频部分电路原理设计、建模、仿真、测试和调试等相关工作，能够指导进行RF布线；有AD/DA, PLL,PA,LNA,MIXER,Filter，VGA 电路设计经验尤佳。

• 掌握常用射频测试仪器，如网络分析仪，频谱分析仪，信号发生器等；掌握射频电路的测试方法。

• 熟悉EDA软件,Cadence Spectre，ADS，HFSS等。

• 具有创新能力、良好的沟通能力和团队精神。

• Troubleshoot and administer engineering systems which are built up by Unix/Linux/Solaris systems.

• Troubleshoot and manage network structure, it covers WAN, LAN, VPN.

• Daily monitor system running status, system performance.

• Make regular tape backup and plan recovery test.

• Work with team members to optimize network and systems.

• Bachelor of Computer science or related subjects, over 4 years of System Administrator experience.

• In-depth knowledge of Unix/Linux systems, TCP/IP and network security, have rich experiences on NIS, NFS, SAN and NAS storage.

• Experience with scripting for Solaris and Linux based OS.

• Experience with virtualization technologies (VMware ESX/ESXi), NetApp management is preferred.

• Strong capability and awareness of leaning new technologies.

• Self-motivated and team spirit.

• Fluent in English reading and writing. Experience in multinational company is preferred.

• Manage local team of product and application engineers.

• Develop expert level understanding of IP product offerings, and define new feature or product specification based on in-depth understanding of customer requirements.

• Working with sales and customers in technical evaluation and managing the engagement.

• Maintain good customer relationship, support and resolve their issues, identify needs and new opportunities.

• Perform technical training, presentation, and demo to customers, sales, and engineers.

•  

• 6+ years hands-on experience in product or application engineering in the relevant semiconductor area, experience in managing a team is a plus.

• Familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation).

• Working experience in one of the fields in graphics, video, multi-media, image processing or computer vision.

• Skillful in analysis, generate ideas, and provide innovative solutions to solve technical problems.

• Self-motivated, team work, and good communication skills in English.

• Develop expert level understanding of IP product offerings, including capabilities, competitiveness, and the applications.

• Define new feature or product specification based on in-depth understanding of customer requirements.

• Engage with customer in technical evaluation, provide respond to technical requests or questions, and managing the engagement.

• Maintain good customer relationship, support and resolve their issues, identify needs and new opportunities.

• Perform technical training, presentation, and demo to customers, sales, and engineers.

• 4+ years hands-on experience in product or application engineering in the relevant semiconductor area.

• Familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation).

• Working experience in one of the fields in graphics, video, multi-media, image processing or computer vision.

• Skillful in analysis, generate ideas, and provide innovative solutions to solve technical problems.

• Self-motivated, team work, and good communication skills in English.

• Play an important role in defining video IP spec and devising Video IP architecture.

• Develop challenging modules including module spec definition, macro architecture design, RTL coding, C coding, simulation and synthesis.

• Carry out IP level verification or IP blocks integration/implementation.

• Help junior engineers to solve technical issues.

• Support customers regarding Video IP application.

• Bachelor degree or above in EE.

• 5+ years of work experience in related areas.

• Good knowledge of some of the following general IP: H.264, H.265, MPEG, JPEG, AVS, AVS+ decoder & encoder and so on.

• Skilled in the field of digital circuit design, whole digital design flow and EDA tools.

• Skilled in some of the following disciplines: RTL coding, C coding, Catapult C coding, simulation, synthesis/DFT/STA. Knowledge about catapult C design flow is a plus.

• Key member in at least one mature silicon proven video IP.

• Fluent in both English and Chinese.

• Self motivated, good communication skill and team work spirit.

• Play a leadership role in defining video IP spec and devising Video IP architecture.

• Develop challenging modules including module spec definition, macro architecture design, RTL coding, C coding, simulation and synthesis.

• Carry out IP level verification or IP blocks integration/implementation.

• Be responsible for project progress control and design schedule.

• Help engineers to solve technical issues.

• Support customers regarding Video IP application.

• Bachelor degree or above in EE.

• 7+ years of work experience in related areas.

• Good knowledge of some of the following general IP: H.264, H.265, MPEG, JPEG, AVS, AVS+ decoder & encoder and so on.

• Skilled in the field of digital circuit design, whole digital design flow and EDA tools.

• Skilled in some of the following disciplines: RTL coding, C coding, Catapult C coding, simulation, synthesis/DFT/STA. Knowledge about catapult C design flow is a plus.

• Leader at least one mature silicon proven video IP.

• Fluent in both English and Chinese.

• Good customer communication skill.

• Self motivated, good communication skill and team work spirit.

• GPU & Vision architectural modeling and analysis of graphics/compute/vision algorithms and features.

• Document/design/develop tools to validate models and analyze performance.

• Develop tests, test plans, and testing infrastructure for new graphics/compute/vision architectures/features.

• Co-work with RTL team, cross-validate model and RTL.

• Master or PHD degree in Graphics, CS, EE, or Math.

• Strong C/C++ programming skills, perf/python programming skills is a plus.

• Excellent in mathematics or solid understanding of graphics pipeline (such as DX/OpenGL)/compute (such as openCL/Cuda/DX Compute) / Vision (such as OpenVX/DL/NN/TensorFlow).

• Strong background in computer architecture is a good plus.

• Experience in upstream industry (such as game-engine/modeling for algorithm of parallel computation/HPC/vision applications) is good plus.

• Experience in performance analysis for GPU and vision processor is a big plus.

• Good written and spoken English.

• Self motivated, team work, and good communication are a must.

• Capable of independently contributing to and working on the design/implementation/verification of passes of certain intermediate-language representation level of backend compiler for GPU/DSP targets.

• Capable of designing/implementing optimization algorithm for our world-class optimizing compiler.

• Work closely with driver engineers/hardware architecture engineers/tool engineers to solve functional verification and performance tuning.

• Work closely with QA/PM team to solve software release/customer issues under pressure.

• Experience with compiler development in academia or industry environment.

• Knowledge of modern compiler technologies, including intermediate-language representation, platform dependent/independent optimizations, functional transformation, code generation, etc.

• Knowledge of compiler-related data structures and algorithms such as graph algorithms, analysis and optimization algorithms.

• Familiarity with graphics shading languages, LLVM and GPU architectures a definite plus.

• Experience of working with a large code base with C/C++, assembly programing language.

• MS or PhD in Computer Science or Computer Engineering.

• Design top-of-the-line graphics/Vision processors, including specification, architecture, micro-architecture, implementation (using Verilog), and verification.

• 3+ years hands-on experience.

• Programming skills in Verilog HDL.

• Must be familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation).

• Highly motivated and skillful at solving difficult technical problems.

• Knowledge of computer graphics and low-power design techniques is a plus.

• Experience of OpenCL VX is a plus.

• Experience of Neural Network and Tensor Processing design is a plus.

• Design top-of-the-line graphics/Vision processors, including specification, architecture, micro-architecture, implementation (using Verilog), and verification.

• 3+ years hands-on experience.

• Programming skills in Verilog HDL.

• Must be familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation).

• Highly motivated and skillful at solving difficult technical problems.

• Knowledge of computer graphics and low-power design techniques a plus.

• Experience of memory controller or AXI bus design is a plus.

• Design top-of-the-line image processors, including specification, architecture, micro-architecture, implementation (using Verilog), and verification.

• 3+ years hands-on experience.

• Programming skills in Verilog HDL.

• Must be familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation).

• Highly motivated and skillful at solving difficult technical problems.

• Knowledge of computer graphics and low-power design techniques a plus.

• Experience of image process design is a plus.

• Develop challenging analog circuits independently, including circuit design, simulation, testing, debugging and improvement.

• Determine system requirement, define project specifications according to customer’s requirement.

• Lead the project development.

• Contribute phenomenally to problem solving in circuit design, testing and debugging.

• Supervise layout development.

• Provide technical support for Customer/FAE/Sales.

• Master degree or above in EE.

• With 2+ years of work experience in the analog circuit related areas.

• Good knowledge in at least one of the following disciplines: VCO, PLL, DLL, PCIex, USB, SATA, LVDS, HDMI, etc.

• Experience on high speed SerDes architecture or circuit is a plus.

• Good understanding about the entire development flow of IC design, including process, package, testing, etc.

• Fluent in both English and Chinese.

• Self motivated, good communication skill and team work spirit.

• Design and develop Embedded System in ASIC and SoC projects, including design and debug hardware and firmware like BSP, Drivers and API on board level.

• Carry out System/Sub-system/IP FPGA verification/validation for IC and SoC design.

• Perform in house test for IC and SoC products.

• Work with project members to determine system requirement, design prototyping and support customers in product applications; Play an important role in SoC and System project development.

• Provide technical support for Customer/FAE/Sales.

• Bachelor degree or above in EE, CS or Automation.

• 2+ years of work experience in the related areas.

• Track record of successfully silicon proven System or SoC projects.

• Good architecture knowledge about at least 2 types of the following SoC systems: ZSP/ARM/8051/Power PC and peripheral systems.

• Good knowledge/experience in ZSP/8051/ARM embedded system development, including BSP, Device Driver and API development.

• Clear understanding of hardware/software interaction and system level tradeoffs.

• Good knowledge/experience in C/C++ and ASM; FPGA/ASIC prototyping/demo system design, development, synthesis and application reuse; debugging board, firmware and FPGA, etc. on system level.

• Familiar with lab equipment.

• Fluent in both English and Chinese.

• Self motivated, good communication skill and team work spirit.

• Port Embedded Linux/Android for SoC chip, develop Linux driver and API for application.

• Work with project members to determine system requirement, design prototyping and support customers in product applications.

• BSEE/CS 3+ years embedded software development experience in Linux.

• Good knowledge/experience in ARM/PowerPC embedded system development, PowerPC/ARM processor architecture and PowerPC/ARM Compiler.

• Experienced in the drivers of CPU peripheral like LCD, NAND, flash, I2C, SPI, etc.

• Experienced in embedded system design.

• Working knowledge of the GNU tool chain for software development.

• Android development experience and hardware related knowledge will be a plus.

• Strong problem solving and analytical skills.

• Self-motivated and good team player.

• Good written and spoken English.

• Comprehend the SoC clock structure and working mode and prepare the SDC file for SoC design.

• Prepare the DFT plan for the SoC design.

• SCAN/MBIST/BSD insertion and synthesize methodology for Flatten / Hierarchical design.

• Pre/Post simulation for test patterns.

• Cooperate with timing engineer for timing signoff (STA).

• Analog IP test implementation and simulation.

• Support ATE engineer for chip testing debug, and analyze ATE log file to locate root cause of failure.

Formal check of RTL and netlist.

• Bachelor's degree or above, major in EE, CS or relevant.

• Above 5years work experience to the one with Bachelor's degree and above 3years with Master's degree is required for Senior Engineer position.

• Skilled in SoC PPA, better for low power design.

• Improve low test coverage to achieve higher coverage.

• Skilled in csh/perl/tcl scripts.

• Be familiar with concept of SoC and P&R physical implementation.

• Fluent in both English and Chinese.

• Good team work spirit.

• Understanding the expected functionality of designs.

• Developing testing and regression plans.

• Designing and developing verification environment.

• Running RTL and gate-level simulations/regression.

• Code/functional coverage development, analysis and closure.

• Minimum of 3 years design/verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).

• Knowledge in ASIC/FPGA design process and verification tools/env ( UVM/OVM…).

• Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).

• Scripting and automation skills (tcl, perl, makefile etc) a plus.

• Familiar with C/C++.

• Knowledge of DDR/Video/ARM/USB/PCIE , Low Power Verification with UPF and design experience is a plus.

• Experience in CPU/DSP verification, including test plan and test bench development, test case development and test coverage assessment. and Knowledge of computer architecture and micro-architecture (pipeline, out-of-order, cache) is a plus.

• Additional qualifications include: Good IC verification skills and basic knowledge of logic or circuit design, good communication and problem solving skills.

• Independent and self-managing.

• Play an important role in defining chip spec and devising chip architecture.

• Develop challenging modules including module spec definition, macro architecture design, RTL coding, simulation and synthesis.

• Carry out chip level verification or chip integration/implementation.

• Help junior engineers to solve technical issues.

• Support customers regarding chip applications.

• Bachelor degree or above in EE, 3+ years experience.

• Good knowledge of some of the following general IP: CPU/DSP, AMBA, DDR/SDRAM, video (HEVC, MIPI…), parallel/serial peripheral module, DMA, interrupt, timer, GPIO.

• Good skill in the field of digital circuit design, whole digital design flow and EDA tools;

• Key member in at least one successfully silicon proven challenging project.

• Fluent in both English and Chinese.

• Self motivated, good communication skill and team work spirit.

• Responsible for SDC and UPF/CPF development and debug.

• Focus on design floor planning, power planning, IO planning, placement & CTS and routing, handling timing and congestion issue during project implementation.

• IP level and chip level physical verification and DFM rule checking.

• Power analysis and IR drop/EM analysis for both static and dynamic.

• Strong capability in timing analysis, and independently handle all timing issues from netlist/RTL to GDS process.

• Responsible for timing signoff for all functional modes and concerns, and work closely with DFT engineer for scan modes timing closure.

• Work closely with package team and IO team regarding IO placement to address IO ESD, SSO and chip power supplement concerns.

• Communicate with customer as well as AE or sales.

• Bachelor’s degree or above in EE.

• Skilled in csh/perl/tcl.

• 2+ years work experience in relevant areas is required for Senior Engineer position.

• Good knowledge in at least one of the following disciplines: high speed chip P&R skills, advance node chip P&R, hierarchical flow or low power P&R implementation, physical layout & verification.

• Rich experience on timing/noise violation fixing and CTS tree synthesis.

• Good understanding about entire development flow of IC design.

• Good understanding about FE design, process, package, testing, etc.

• Fluent in both English and Chinese.

• Self motivated, good communication skill and team work spirit.