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首页 IP 组合 MIPI DPHY

This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.1/v1.2”, which consists of Bi-directional 1-Clock and 4-Data lanes. It can support both Master and Slave side. Each lane supports 2.5Gbps in High-Speed mode and 10Mbps/lane in Low-Power escape mode. The target applications are CSI-2 and DSI physical layers.

Features

  • Silicon proven in 22, 28, 55, 110nm from Global Foundries, Samsung and SMIC

  • Compliant to the MIPI D-PHY spec v1.1 (SEC28/SMIC55/SMIC110)

  • Lane type:1 clock + 4 data, bi-directional

  • Built-in self test function

  • Junction temperature range: -40°C~25°C~125°C


  • Data rate per lane: High-Speed mode 80M~1.5/2.5G bps, Low-Power mode 10Mbps

  • Support Reverse Escape mode (High-speed reverse is not supported)

  • Compliant to the MIPI D-PHY spec v1.2 (GF22)

  • On-chip differential 100Ω terminations with calibration

  • Support wire-bond and flip-chip application




MIPI DPHY.jpg

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