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首页 IP 组合 MIPI DPHY-TX

This is a DPHY Master IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of 1-Clock and 4-Data lanes. Each data lane can support HS and LP Escape modes (LPDT, Trigger, ULPS) in forward direction. The supported data rate per lane is 2.5Gbps in High-Speed mode and 10Mbps in Low-Power escape mode. Only data lane0 is bi-directional and can additionally support Turnaround and LP Escape mode (LPDT and Trigger) in reverse direction. The target applications are CSI-2 device and DSI host physical layers.

Features

  • Data rate per lane: High-Speed mode 80M~2.5G bps, Low-Power mode 10Mbps

  • Silicon proven in GlobalFoundries 22FDX process

  • Compliant to the MIPI D-PHY spec v1.2

  • Support HiSPi-SLVS TX compatible mode

  • Lane type:1 clock + 4 data (D0 is bi-dir)

  • On-chip differential 100Ω terminations with calibration

  • Support for DPHY Ultra Low Power State

  • Built-in self test function

  • Supply voltage: 1.8V±10%, 0.8V±10%

  • Junction temperature range: -40°C~25°C~125°C

  • Support wire-bond and flip-chip package type

MIPI DPHY-TX.jpg

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