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The analog-to-digital converter is a differential high speed low power IP which uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution. The ADC includes a core internal SAR ADC which consists of sample/hold circuits, a capacitive DAC, a comparator and logic control circuits.

The ADC is designed with high dynamic performance for input signal frequencies up to Nyquist.

It is perfectly suitable for broadband communication applications.

Features

  • Silicon proven in 22, 28, 55nm from SMIC,Global Foundries and Samsung

  • Resolution: 10-bit/12-bit

  • Data Rate: 40Msps/64Msps

  • Differential-ended Mode

  • Analog Input Range

    -  10-bit:VREFH to VREFL

    -  12-bit:1.1Vpp

  • DNL: ±1.5 LSB, INL: ±3 LSB

  • Excellent Dynamic Parameters

    -  SFDR @ Fin=5MHz: 67dbc/10-bit;75dbc/12-bit;

    -  SNR:56dbc/10bit;60dbc/12bit

  • Low Power Consumption:

    -  1.2mA@40MSPS,10-bit

    -  1.5mA@64MSPS,12-bit

VIDEO_ADC.jpg

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